#include "ieee_fun_types.h" #include #include int initAndConfigureAD114( int branch, int crate, int slot, int virtID, int lld, int uld, int dcOffset ) { /* setup and configure a Ortec AD411 ADC */ /****************** SET UP nth Ortec AD411 ADC ***********************/ /* 0x5F00 = 1001 1111 0000 0000 B16 =1 => Overflow-suppresion enable when 0 B15 0 Notused B14 0 CAMac LAM enable when 1 B13 =1 => Singles mode --- B12 =1 => Enable Master Gate when 0, Master Gate ignored when 1 B11 =0 => Enable Local Gate when 0, ignor local gate when 1 B10 =0 => ECL port enable : 0=ECL prot readout enabled, 1 Camac readout enabled B9 =1 => Zero-suppression enable : when 0 ADC with zeros for are skipped during readout --- b1 to b8 => Virt station number */ int ext; int subad,function,qres; unsigned short dataw[2]={0,0}; float flld=0.0, fuld=0.0, dcoffset=0; int err; err=0; /* clear error flag to return */ printf("\n\n Initializing AD411 in crate=%d as ID=%d", crate, virtID); /* Clear module */ subad=0; cdreg(&ext,branch,crate,slot,subad); cssa(9,ext,dataw,&qres); printf(" (using slot=%d) ",slot); /* Write to control register and read back */ dataw[0]=0x1801; /* standard */ dataw[0]=0x8901; /* fails */ dataw[0]=0x8801; /* fails */ dataw[0]=0x9801; dataw[0]=0x9901; dataw[0]=0x1901; dataw[0]=0x0901; dataw[0]=0x0801; dataw[0]=0x1801; /* standard */ dataw[0] = 0x1800 + virtID; cssa(16,ext,dataw,&qres); /* Using FERA */ cssa(0,ext,&dataw[0],&qres); printf("\n ADC Control Register: 0x%x", dataw[0]); dataw[0]=0x00D7; dataw[0]= 0x00FF & lld; flld= 2.0*dataw[0]; printf("\n Write %X to LLD translates to %f mV.", dataw[0],flld); subad=0; function=17; cdreg(&ext,branch,crate,slot,subad); cssa(function,ext,&dataw[0],&qres); dataw[0]=0x001F; dataw[0]=0x00FF & uld; flld= 8.0*dataw[0] + 8500.0; printf("\n Write %X to ULD translates to %f mV.", dataw[0],flld); subad=1; function=17; cdreg(&ext,branch,crate,slot,subad); cssa(function,ext,&dataw[0],&qres); dataw[0]=0x0080; /* power on default */ dataw[0]=0x00FF & dcOffset; dcoffset= 0.312*((dataw[0] & 0xFF) - 128); printf("\n Write %X to dc offset which translates to %f ?V.", dataw[0],dcoffset); subad=2; function=17; cdreg(&ext,branch,crate,slot,subad); cssa(function,ext,&dataw[0],&qres); /* Read lower level discriminator setting */ subad=0; cdreg(&ext,branch,crate,slot,subad); cssa(1,ext,&dataw[0],&qres); flld= 2.0*(dataw[0] & 0xFF); printf("\n ADC1 LLD: 0x%x translates to %f mV.", (dataw[0] & 0xFF) , flld); /* Read upper level discriminator setting */ subad=1; cdreg(&ext,branch,crate,slot,subad); cssa(1,ext,&dataw[0],&qres); fuld = 8.0*(dataw[0] & 0xFF) + 8500.0; printf("\n ADC1 ULD: 0x%x translates to %f mV.", dataw[0] & 0xFF, fuld); /* Read input dc offset */ subad=2; cdreg(&ext,branch,crate,slot,subad); cssa(1,ext,&dataw[0],&qres); dcoffset = 0.312*((dataw[0] & 0xFF) - 128); printf("\n ADC1 dc offset: 0x%x translates to %f ?V.", dataw[0] & 0xFF, dcoffset); printf("\n"); return 0; } int initAndConfigLeCroy4302Memory( int branch, int crate, int slot ) { int err; int iloop; int ext; int subad,function,qres; unsigned short dataw[2]={0,0}; err = 0; /***************** SET UP the LeCroy 4302 FERA memory ********************/ printf("\n Initializing 4302 buffer memory"); function=0; subad=1; cdreg(&ext,branch,crate,slot,subad); dataw[0]=0x1; cssa(17,ext,dataw,&qres); /* Set 4302 to CAMAC mode*/ printf(" (using slot=%d) ",slot); subad=0; cdreg(&ext,branch,crate,slot,subad); dataw[0]=0x1; cssa(26,ext,dataw,&qres); /* Set 4302 to enable LAM*/ dataw[0]=0x0; cssa(17,ext,dataw,&qres); /* Set 4302 to first memory address */ printf("\n Writing 0s to all memory addresses."); for(iloop=0; iloop<16385; iloop++){ cssa(16,ext,dataw,&qres);} /* Write 0x0 to all memory addresses */ cssa(17,ext,dataw,&qres); /* Set 4302 to first memory address again */ cssa(10,ext,dataw,&qres); /* Test and clear the LAM on 4302 */ printf("\n 4302 Test and clear LAM qres = %d ", qres); subad=1; cdreg(&ext,branch,crate,slot,subad); dataw[0]=0x3; cssa(17,ext,dataw,&qres); /* Set 4302 ECL mode enabled */ cssa(1,ext,&dataw[0],&qres); /* Read mode */ printf("\n 4302 buffer mode is = %X",dataw[0]); printf("\n"); return 0; } int initAndConfigLeCroy4300ADC( int branch, int crate, int slot, int virtID, int pedestal ) { int err; int iloop; int ext; int subad,function,qres; unsigned short dataw[2]={0,0}; err = 0; function = 0; printf("\n Initializing 4300 ADC in crate = %d", crate); subad=0; printf(" Issue a Clear Module "); cdreg(&ext,branch,crate,slot,subad); cssa(9,ext,dataw,&qres); printf(" (using slot=%d) ",slot); /* write a status word register value */ dataw[0]=0x0404; dataw[0]=0x0604; /* dataw[0]=0x0704; */ dataw[0] = 0x0700 + virtID; cssa(16,ext,dataw,&qres); if ( qres == 0 ) { printf("\n 4300 ADC was busy when writing status word\n Exit with error. \n"); return 1; } /* set pedestals all to zero */ for (iloop=0; iloop<16; iloop++) { subad = iloop; cdreg(&ext,branch,crate,slot,subad); dataw[0]= pedestal; cssa(17,ext,dataw,&qres); if ( qres == 0 ) printf(" 4300 signaled busy at write to pedestal %d\n", iloop); } subad=0; cdreg(&ext,branch,crate,slot,subad); cssa(0,ext,&dataw[0],&qres); printf("\n 4300 control register = %X Q=%d",dataw[0],qres); cssa(9,ext,dataw,&qres); printf("\n"); return 0; }