Design Overview for top_tdc_controller_pad

PropertyValue
Project Name:c:\documents and settings\tofpet\my documents\lbnl_cfd-hptdc\vhdl\pet_tdc_controller
Target Device:xc3s1000
Report Generated:Thursday 08/03/06 at 14:36
Printable Summary (View as HTML)top_tdc_controller_pad_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:22615,3601% 
Number of 4 input LUTs:22315,3601% 
Logic Distribution:    
Number of occupied Slices:1897,6802% 
Number of Slices containing only related logic:189189100% 
Number of Slices containing unrelated logic:01890% 
Total Number 4 input LUTs:27715,3601% 
Number used as logic:223   
Number used as a route-thru:54   
Number of bonded IOBs:12033336% 
Number of Block RAMs:1244% 
Number of GCLKs:5862% 
Number of DCMs:2450% 

Performance Summary

PropertyValue
Final Timing Score:0
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
All Constraints Met   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentThursday 08/03/06 at 14:35
Translation ReportCurrentThursday 08/03/06 at 14:36
Map ReportCurrentThursday 08/03/06 at 14:36
Pad ReportCurrentThursday 08/03/06 at 14:36
Place and Route ReportCurrentThursday 08/03/06 at 14:36
Post Place and Route Static Timing ReportCurrentThursday 08/03/06 at 14:36
Bitgen ReportCurrentThursday 08/03/06 at 14:36