Property | Value |
Project Name: | u:\hptdc\vhdl\pet_tdc_controller |
Target Device: | xc3s1000 |
Report Generated: | Thursday 11/10/05 at 17:06 |
Printable Summary (View as HTML) | top_tdc_controller_summary.html |
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops: | 14 | 15,360 | 1% | |
Number of 4 input LUTs: | 9 | 15,360 | 1% | |
Logic Distribution: | ||||
Number of occupied Slices: | 11 | 7,680 | 1% | |
Number of Slices containing only related logic: | 11 | 11 | 100% | |
Number of Slices containing unrelated logic: | 0 | 11 | 0% | |
Total Number 4 input LUTs: | 20 | 15,360 | 1% | |
Number used as logic: | 9 | |||
Number used as a route-thru: | 11 | |||
Number of bonded IOBs: | 104 | 333 | 31% | |
Number of GCLKs: | 2 | 8 | 25% | |
Number of DCMs: | 1 | 4 | 25% |
Property | Value |
Number of Unrouted Signals: | All signals are completely routed. |
Number of Failing Constraints: | 0 |
Constraint(s) | Requested | Actual | Logic Levels |
No Constraints Found |
Report Name | Status | Last Date Modified |
Synthesis Report | Current | Thursday 11/10/05 at 17:06 |
Translation Report | Current | Thursday 11/10/05 at 17:06 |
Map Report | Current | Thursday 11/10/05 at 17:06 |
Pad Report | Current | Thursday 11/10/05 at 17:07 |
Place and Route Report | Current | Thursday 11/10/05 at 17:07 |
Post Place and Route Static Timing Report | Current | Thursday 11/10/05 at 17:07 |
Bitgen Report | Current | Thursday 11/10/05 at 17:07 |