Design Overview for top_tdc_controller

PropertyValue
Project Name:u:\hptdc\vhdl\pet_tdc_controller
Target Device:xc3s1000
Report Generated:Thursday 11/10/05 at 17:06
Printable Summary (View as HTML)top_tdc_controller_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:1415,3601% 
Number of 4 input LUTs:915,3601% 
Logic Distribution:    
Number of occupied Slices:117,6801% 
Number of Slices containing only related logic:1111100% 
Number of Slices containing unrelated logic:0110% 
Total Number 4 input LUTs:2015,3601% 
Number used as logic:9   
Number used as a route-thru:11   
Number of bonded IOBs:10433331% 
Number of GCLKs:2825% 
Number of DCMs:1425% 

Performance Summary

PropertyValue
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
No Constraints Found   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentThursday 11/10/05 at 17:06
Translation ReportCurrentThursday 11/10/05 at 17:06
Map ReportCurrentThursday 11/10/05 at 17:06
Pad ReportCurrentThursday 11/10/05 at 17:07
Place and Route ReportCurrentThursday 11/10/05 at 17:07
Post Place and Route Static Timing ReportCurrentThursday 11/10/05 at 17:07
Bitgen ReportCurrentThursday 11/10/05 at 17:07