Design Overview for top_tdc_controller_pad

PropertyValue
Project Name:c:\documents and settings\tofpet\desktop\lbnl hptdc board\vhdl\pet_tdc_controller
Target Device:xc3s1000
Report Generated:Monday 01/14/08 at 17:29
Printable Summary (View as HTML)top_tdc_controller_pad_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:33215,3602% 
Number of 4 input LUTs:35015,3602% 
Logic Distribution:    
Number of occupied Slices:3097,6804% 
Number of Slices containing only related logic:309309100% 
Number of Slices containing unrelated logic:03090% 
Total Number 4 input LUTs:40115,3602% 
Number used as logic:350   
Number used as a route-thru:51   
Number of bonded IOBs:12033336% 
Number of Block RAMs:1244% 
Number of GCLKs:5862% 
Number of DCMs:2450% 

Performance Summary

PropertyValue
Final Timing Score:3343
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints (total failing = 1)

Constraint(s)RequestedActualLogic Levels
* TS_aa = MAXDELAY FROM TIMEGRP "FFS" TO TIMEGRP "FFS" 9 ns 9.000ns9.635ns5

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentMonday 01/14/08 at 17:27
Translation ReportCurrentMonday 01/14/08 at 17:28
Map ReportCurrentMonday 01/14/08 at 17:28
Pad ReportCurrentMonday 01/14/08 at 17:28
Place and Route ReportCurrentMonday 01/14/08 at 17:28
Post Place and Route Static Timing ReportCurrentMonday 01/14/08 at 17:29
Bitgen ReportCurrentMonday 01/14/08 at 17:29