Property | Value |
Project Name: | c:\documents and settings\tofpet\desktop\lbnl hptdc board\vhdl\pet_tdc_controller |
Target Device: | xc3s1000 |
Report Generated: | Monday 01/14/08 at 17:29 |
Printable Summary (View as HTML) | top_tdc_controller_pad_summary.html |
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops: | 332 | 15,360 | 2% | |
Number of 4 input LUTs: | 350 | 15,360 | 2% | |
Logic Distribution: | ||||
Number of occupied Slices: | 309 | 7,680 | 4% | |
Number of Slices containing only related logic: | 309 | 309 | 100% | |
Number of Slices containing unrelated logic: | 0 | 309 | 0% | |
Total Number 4 input LUTs: | 401 | 15,360 | 2% | |
Number used as logic: | 350 | |||
Number used as a route-thru: | 51 | |||
Number of bonded IOBs: | 120 | 333 | 36% | |
Number of Block RAMs: | 1 | 24 | 4% | |
Number of GCLKs: | 5 | 8 | 62% | |
Number of DCMs: | 2 | 4 | 50% |
Property | Value |
Final Timing Score: | 3343 |
Number of Unrouted Signals: | All signals are completely routed. |
Number of Failing Constraints: | 0 |
Constraint(s) | Requested | Actual | Logic Levels |
* TS_aa = MAXDELAY FROM TIMEGRP "FFS" TO TIMEGRP "FFS" 9 ns | 9.000ns | 9.635ns | 5 |
Report Name | Status | Last Date Modified |
Synthesis Report | Current | Monday 01/14/08 at 17:27 |
Translation Report | Current | Monday 01/14/08 at 17:28 |
Map Report | Current | Monday 01/14/08 at 17:28 |
Pad Report | Current | Monday 01/14/08 at 17:28 |
Place and Route Report | Current | Monday 01/14/08 at 17:28 |
Post Place and Route Static Timing Report | Current | Monday 01/14/08 at 17:29 |
Bitgen Report | Current | Monday 01/14/08 at 17:29 |